Por favor utiliza este link para citar o compartir este documento: http://repositoriodigital.academica.mx/jspui/handle/987654321/81871
Título: Electrical Parameters Extraction of CMOS Floating-Gate Inverters
Palabras clave: FG-inverter
neuMOS
floating-gate
Fecha de publicación: 16-Jul-2012
Editorial: Ingeniería, investigación y tecnología
Descripción: This work provides an accurate methodology for extracting the floating-gate gain factory, of CMOS floating-gate inverters with a clock-driven switch for accessing temporarilly to the floating-gate. With the methodology proposed in this paper, the γ factor and other parasitic capacitances coupled to the floating-gate can be easily extracted in a mismatch-free approach. This parameter plays an important role in modern analog and mixed-signal CMOS circuits, since it limits the circuit performance. Theoretical and measured values using two test cells, fabricated in a standard double poly double metal CMOS AMI-ABN process with 1.2 µm design rules, were compared. The extracted parameters can be incorporated into floating-gate PS pice macromodels for obtaining accurate electrical simulation.
Other Identifiers: http://www.scielo.org.mx/scielo.php?script=sci_arttext&pid=S1405-77432010000300007
Aparece en las Colecciones:Ingeniería, Investigación y Tecnología

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